1. Technical Field
This disclosure relates to semiconductor fabrication, and more particularly, to a method for reducing the risk of cracks in semiconductor chips.
2. Description of the Related Art
Semiconductor chips are formed on a silicon wafer. The chips are placed adjacent to one another on the wafer, and after fabrication processes are completed, the wafer is diced by cutting the wafer along kerfs. This separates the chips from each other. The dicing processes may induce stress into the chips. This stress may cause stress cracks to form through the semiconductor chip structure. Cracks may also form due to latent stresses in the semiconductor chip structure. Cracks typically form along interfaces between, for example, metal structures and dielectric materials. Some portions of the semiconductor structures are particularly susceptible to crack propagation.
Referring to FIG. 1A, a partial cross-sectional view of a metal structure is shown in accordance with the prior art. A substrate 10 includes diffusion regions 12, which are part of devices or components, such as transistors, capacitors, resistors, etc. A first level contact 14 connects diffusion region 12 to a first metal line 16. First metal line 16 runs into and out of the plane of the page, and is employed, for example, in making connections between devices on the substrate level or to higher metal layers. Another contact 18 connects metal line 16 to a metal line 20, which also runs into and out of the plane of the page. Contact 22 is employed for making connections between metal line 20 and higher metal layers. In this case higher metal layers include a terminal via (TV) 24 which is connected to metal line 20 by a contact 22. Terminal via 24 is typically employed for providing a test probe contact area and an area for connecting lead wires for electrically connecting the chip to a leadframe for packaging the chip.
The structure shown in FIG. 1A is susceptible to crack propagation. Stresses present in the chip or induced by processes, such as dicing, causes cracks to propagate along the structure in areas 26. Cracks form at the interface between dielectric material 28, for example, silicon dioxide, and metal lines/contacts. Cracks, which propagate down to substrate 10, have the potential for causing chip failures over time. Cracks also expose metal lines and contacts to ambient environments, which can cause corrosion/oxidation which degrade chip performance.
Referring to FIG. 1B, a top view taken at section line 1Bxe2x80x941B of the prior art structure of FIG. 1A is shown. Contacts 14 (18 and/or 22) are circular in shape and contact a small area of metal lines (e.g., 16 and 20) and/or terminal via (24). This area mismatch lends itself to stress concentrations, which may be detrimental to the reliability of the chip over time.
Therefore, a need exists for an improved crack stop design, which provides additional contacts between metal lines with a different geometry. A further need exists for a crack stop design, which includes an air crack stop.
A semiconductor chip, in accordance with the present invention, includes a substrate and a crack stop structure. The crack structure includes a first conductive line disposed over the substrate and at least two first contacts connected to the substrate and to the first conductive line. The at least two first contacts are spaced apart from each other and extend longitudinally along a length of the first conductive line. A second conductive line is disposed over a portion of the first conductive line, and at least two second contacts are connected to the first conductive line and the second conductive line. The at least two second contacts are spaced apart from each other and extend longitudinally along a length of the second conductive line. The crack stop structure provides multiple contacts at each level to improve crack resistance.
Another semiconductor chip of the present invention, includes a substrate and a crack stop structure. The crack stop structure includes a first conductive line disposed over the substrate, and at least two first contacts are connected to the substrate and to the first conductive line. The at least two first contacts are spaced apart from each other and extend longitudinally along a length of the first conductive line. A second conductive line is disposed over a portion of the first conductive line, and at least two second contacts are connected to the substrate. The at least two second contacts are spaced apart from each other and extend longitudinally along a length of the first conductive line. A dielectric material surrounds the crack stop structure, and the dielectric material includes an air-filled trench over the second conductive line to improve crack growth resistance.
In alternate embodiments, the at least two first contacts may include three contacts. The at least two second contacts may include three contacts. The chip may include a dielectric material surrounding the crack stop structure, and the dielectric material may include an air-filled trench over the second conductive line. The second conductive line may include a terminal via for testing the chip.
The chip may further include a third conductive line disposed over a portion of the second conductive line, and at least two third contacts connected to the second conductive line and the third conductive line, the at least two third contacts being spaced apart from each other and extending longitudinally along a length of the third conductive line. The third conductive line may include a terminal via. The first and second metal lines and the at least two first contacts and the at least two second contacts may form a serpentine structure. The serpentine structure is preferably located adjacent to a dicing channel of the chip. The at least two first contacts and the at least two second contacts may extend over the entire length of the first metal line.
These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.